SBC-UADI Notes
The SBC-UADI is single board computer based on the microcontroller MSP430F149 from TI.
It supports the following protocols:
1- MIL-STD-1553
2- ARINC 2 WIRES PROTOCOLS: 429 , 575, 562 , 572 , 582, 615.
3- ARINC 708 , 453
4- RS232
Compiler:
BMC develop it system based on IAR C compiler. The programs and workspace included in the CD are based on IAR compiler. The user can get from TI a C compiler for the above processor and from any other company.
Emulator:
BMC use the TI emulator MSP-FET430UIF. It can be purchased directly from TI.
CPU Programming:
There are two ways to program the CPU.
1- Emulator – downloading the code using a 14 pin flat cable to connector H1 on the back of the board
2- TI serial download – on MSPDOWNLOAD sub-directory in the CD the user can program his program using the BAT file. The program must have a TXT format according to TI specifications. It requires the following:
a- a standard RS232 cable from the PC to a 9 pin D-type connector
b- a 10 pin flat cable from the P1 (5x2) header on board to a 9 pin D-type connector
c- Connect two jumpers vertically in J1-PROG 2x2 Header
Please note that with the jumpers, user is not able to use the emulator.
The SBC is delivery without these jumpers – default.
Programming:
BMC deeply suggest to use at the beginning the demo program included in CD - SBC-UADI sub-directory and based on the programs add project functionalities.
1553 Receive Data Interrupt.
The unit uses Port2-7 as interrupt for 1553 receive data. The procedure is located in RECUADI.C module:
__interrupt void P2int(void){
1553 Transmit Data:
The unit has an embedded 1kx16 memory. The user can read or write data using procedures located in FPGA.C module:
1- void ReadSingleDPM (int Address, char *pDATA){
2- void ReadDPM (int Address, char *pDATA, int len){ // len in words
3- void WriteDPM (int Address, char *pDATA, int len){ // len in words
4- void WriteSingleDPM (int Address, char *pDATA){
1553 Operating modes:
The user can select board’s operating mode writing into Control register using procedure: void WriteFPGA (char XAddress, char *pDATA, int len){
RT mode
1- Address -The user can select internal or external address ( P1)
2- Memory segment 1kx16 ( 32 RT each with 32 WORDS) has data to be transmitted to the host-master unit
Jumpers on J3 –J4 define 1553 bus connection:
1- DIRECT COUPLING – jumpers on corners 1-2 & 7-8
2- TRANSFORMER COUPLE – jumpers in the middle 3-4 & 5-6 - Default
Board initialization:
During Power-up operation the FPGA is initialized by a serial PROM. Signal DONE connected to CPU – PORT1-4 shows status: 0- not initialized 1- finish and successful initialization.
On board LED.
The program included in the CD uses the LED as a visual indication for proper initialization (BIT). The board has a 32.768 KHz crystal. An internal timer is initialized for a fast frequency, 3 Hz. After proper initialization it changes for a slower frequency, 1 HZ. Otherwise stays with 3 Hz frequency.
The program test internal data bus and FPGA memory.
