THE WORLD of AVIONICS IN YOUR HAND
BMC IP is available for customers who want to implement the interface inside their system.
The IP can be linked to any FPGA device. It can be configured with single or multiple channels and protocols.
It is part of BMC test procedure to certify the product.
Our advanced MIL-STD-1553 IP core come with a set of enhanced capabilities allowing for your communication bus to have real time digital wiring fault detection and prognosis, so your aircraft will experience minimum downtime.
The cores are suitable for any MIL-STD-1553 application, including direct replacement of existing ICs. It includes multiple receive/transmit buffers for 1553 applications, sub-address filtering, error bit detection and/or injection, programmable conditions for RT status error bit, Long LOOP Test error and many others.
There are a variety of ARINC protocols but the most common is ARINC 429/575/572/582/615.., a 32 bit data protocol. It has a two wire line with true and complement data. The electrical signals use a NRZI format. Some equipment requires a parity bit in the bit stream (odd or even), others do not. BMC-IP has implemented all these conditions.
There also a number of ARINC protocols with 6 wires; 3 signals twisted pair, like ARINC 561, ARINC 571 and ARINC 581. The electrical signals use a NRZ format. BMC-IP supports these protocols as well.
The ARINCs receive/transmit IP interface is based on a 32 cache FIFO each with 32 bit words to protecxt the system from data overlap.
ARINC 453/708 software operates exactly as ARINC 2-6 wires protocols.
ARINC 573/717 has programmable transmit/receive rate; 64/128/256/512 words( 10 bits) p/second and error injection as well. It channel is independently configurable through software and operates according to Harvard biphase protocol.
The BMC ARINC-IP offers UNLIMITED independent transmitters and independent receivers in the same core.
BMC can customize the IP according to customer requirements
BMC IP support provides with the IP the following:
1- A comprehensive user manual.
2- A VHDL gate level model of the target
3- Support ALL Xilinx and Altera families.
4- Extensive source examples code programs written in C.
5- BMC boards design: CAPTURE AND LAYOUT.
For more information contact: bmcIP@bmccorp.com