Author Name(s): Calmon Cozer
Author Job Title(s): Director of Eng.
Company: BMC COMMUNICATIONS CORP.
Author E-mail Address(es):  calmon@bmccorp.com
Lead Author’s Phone Number: 631-256-5903   x 30
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COMBINING MULTIPLE DIGITAL AVIONIC PROTOCOL CONVERTERS INTO A SINGLE BOARD

The versatile UADI ( Universal Avionic Design Interface) enables equipment manufacturers for mil-aero applications to implement systems both faster and more cost effectively.

Since its introduction in 1992, PC/104 has been the most popular embedded-system architecture because of its size, rugged construction, and PC compatibility. Later, for the same reasons the Compact PCI (cPCI) became very popular. There is a premium for size and weight in avionics equipment, making the PC/104 and cPCI boards very attractive solutions for implementing avionic applications which includes communication protocols such as ARINC, MIL-STD-1553, AFDX and others. 

Many highly integrated CPU boards are available on the market for the above mentioned protocols. They include video graphic, hard driver and many other types of controllers.  However, none of these manufacturers have implemented an embedded digital avionic protocol. The reason for this may stem from the fact that avionics is too limited a market to justify development of such a board. 

There are a variety of digital protocols for civil and military applications. However, they are not all compatible, having different transfer data rates, different data frames and different architecture.  Typically, a user selects the appropriate board for each protocol. A system with multiple digital communication protocols requires multiple interface boards.  This may resolve the problem in a limited sense, but affect other issues by creating major limitations in cases where there is no physical space for system upgrades.

The most popular protocol used in civil aircraft is ARINC 429.  It operates at two baud rates: 12.5 KHz or 100 KHz.  It is point to point and has a differential NRZI 10 Vpp signal with a 32 bit word data structure.

For the military, the most common digital communication protocol is known as MIL-STD-1553.  It operates as a network with a master (Bus Controller or BC) and slaves (Remote Terminals or RT), has a data transfer rate of 1 MHz, using a 20 bit word data structure with maximum 33 words in each frame  which is transferred through a transformer coupling. Figure 1 shows data bit structure for BC Command word bit definitions and bus transmission order (Bit Time).

1553 Command Word Structure

Figure 1

RT- ADDRESS – defined which terminal will receive a command

R/T – when set to zero logic Terminal receive data when set to 1 Terminal transmit data.

SUB-ADDRESS – sub-system under required terminal

WORD Count – number of words following the BC command or RT data answer.

The new protocol AFDX or ARINC 664, implemented in the new airplanes AIRBUS 380 and BOEING 787, operates at 10 or 100 MHz, uses Manchester Encoding and Decoding. Access control is gained via Carrier Sense, Multiple Access with Collision Detect (CSMA_CD).

It has the following data structure:

Preamble Field: A 7 bit pattern of alternating ones and zeros which are used to synchronize the receiver clock to the incoming data packet.

START FRAMNE DELIMITER: Start Frame Delimiter Field indicates the beginning of the frame; [10101011].

DESTINATION ADDRESS:  The first bit (Most significant Bit) distinguishes between an individual or group address. The second bit distinguished between locally or globally administered addresses.

SOURCE ADDRESS:  The first bit (Most significant Bit) is reserved and set to zero. The second bit distinguishes between locally or globally administrated addresses.

Length/Frame TYPE:  The field has two meanings; if the value is less 1536 decimal, it indicates the number of logical link control in the data field, if is greater or equal to 1536 decimal the number indicates the client protocol.

DATA – user data

CRC-   at the transmit and receive algorithm each generate CRC values.

                                                    Figure 2 - AFDX  DATA STRUCTURE

Many of today’s microcontrollers offer an impressive combination of integrated features and interfaces, including hardware-based ADCs and DACs, PWM support and a range of serial and parallel interfaces. Popular microcontrollers like 80C196 from Intel provide high speed Input/Output and watchdog timer functionality. The primary limitations of these devices are the quantity and quality of the available interfaces and, of course, most microcontrollers are not field programmable like the 80c196. They are oriented to the most popular protocols like the Asynchronous Communication protocol (UART) and usually transmit at a slower rate. Another limitation is the microcontroller speed, which is normally less than 10 MIPS, making it impossible to handle a per bit single serial fast protocol above 1 MHz.

The problem with microcontrollers is they are sequential machines and are incapable of translating serial to parallel data as well as storing incoming multiple data simultaneously.  They are also too slow to meet the exacting standards of avionic protocols.  The interrupt time required to read data from the internal serial to parallel register, store the data into internal or external memory, set flags, increment pointers and verify multiple conditions (like end of buffer) typically take hundreds of instruction cycles. Usually microcontrollers have more than one UART.  As channels are added to a board, the ability of a regular processor to handle the data transfer lessens.  For example, if an instruction cycle executes in 500 nanoseconds, and it takes 200 instruction cycles to read and store information, the processor will be busy for 100 microseconds. This time is equivalent to 5 incoming words from a MIL-STD-1553 or 500 words from an AFDX bus line.

We have found that an FPGA with dedicated logic and memory capabilities can resolve all of these problems.  The remainder of this paper will describe how this concept makes it possible for the CPU to not only process and analyze data, but provide the versatility to support multiple protocols and/or increase the number of system channels.

The combination of a CPU with a FPGA chip gives a very flexible system solution; the CPU with the operational code to analyze and process data together with the FPGA for I/O operation. Most FPGA’s require an external non-volatile storage memory device to hold the device configuration storage. Following power-up, the FPGA configures itself by downloading the configuration from non-volatile memory.  Often the download is serial and may take hundreds of milliseconds for the download operation to complete. To resolve this and other issues, there are flash programmable microcontrollers.

There are a number of advantages for using a flash microcontroller embedded with the system code and the FPGA configuration: They include:

1-         There is only one device to reprogram for any modification;

2-         The FPGA download configuration is done in parallel mode (CPU data bus), taking a fraction of the time of a serial download (external PROM);

3-         Reducing the number of components in the system, increasing the MTBF, decreasing physical size and significantly cutting board cost;

4 -        The CPU can be programmed through a standard RS232 PC connection. The board can be upgraded with a new software version without removing any portion of the installed equipment;

4-         5- The board can increase the number of avionic serial channels (e.g. ARINC, MIL-STD-1553, etc.) as long as the hardware interface is available. 

NOTE: Item 4 is a very important issue when dealing with avionic applications. Whenever equipment is removed from an aircraft, it must pass through an extensive set of tests before it can be reinstalled.  A field programmable unit avoids the inconvenience (time and money) of a reinstall.

Figure 3 shows system block diagram

The FPGA to be selected must have the following features:

1-         Software programmable

2-         Density large enough to combine all necessary logic capable of supporting multiple protocols. Each protocol design module requires logic which can varies from 50 to 300 internal slices. A FPGA slice combines gate logic and registers. As more slices have the selected device, more protocol modules can be implemented under the same design.

3-         Memory is used for store incoming data and as dual port memory for mailboxes between the host computer and board interface.  FPGA memory cell size can vary between 1K word and 100K words. The selection should be made according to application requirements.

4-         Additional I/O pin signals, capable of interfacing with TTL 5V or 3.3V logic level. This option provides the programmer with the capability to add logic signals for future system upgrades.

5-         Low power

6-         Minimum internal frequency of 200 MHz, which provides the speed to handle the new faster avionic protocols like AFDX (running at a data transfer speed of 100 MHz).

Following are examples of how and where FPGA technologies can benefit application development for the various protocols.

ARINC 429-575-572-561-571-581-etc.

 There are a variety of ARINC protocols but the most common is ARINC 429, a 32 bit data protocol. It has a two wire line with true and complement data. The electrical signals are 10 Vpp with a NRZI format. Some equipment require a parity bit in the bit stream (odd or even), others do not.  The user possessing a single board with a FPGA chip can easily define the word format per channel and change it according to the equipment.

MIL-STD-1553

The 1553 20 bit word combines a Manchester code with 3 bits for synchronization, 16 data bits and with the last bit for odd data parity. The BC-RT Command (picture 1) data transfer sequence is defined as the first word; a command followed by the data.  Some protocols define a data parity error as fatal with no RT response and others as an error (setting the error bit in the RT Status answer). This latter condition is implemented through an internal register that defines a variety of errors which will not block the RT Status response, though setting the error bit in real time. The protocol requires the RT to answer after 9.5 uSEC (class A) or 12 uSEC (class B) from a BC command can be programmable using an internal timer.

Another example is the Long Loop Test used in some equipment. The BC transmits a block of 32 data words to sub address 30 of a specific terminal and performs an enquire at a later time. A transmission of less than 32 words is an error, even if the frame and contents are correct. Other applications can also be easily implemented, such as sub-address (bits 5-9 on a Command-picture 1) filtering, so the resulting information is prevented from being stored in memory.  The user can easily define the error conditions and/or response, and/or sub-address filtering per channel according to the application.

These and many other logic conditions can all be implemented into the FPGA design. The standard board can be configured according to customer requirements and can be changed or upgraded with a single download.

The information transmitted or received is stored in the memory available inside the FPGA. The CPU can read, translate and retransmit data through a different channel using different formats.  It presents a perfect environment for protocol conversion applications or for use as a repeater to enhance1553 signals. A single board computer using the flash CPU with a FPGA chip can be customized for a variety of protocol translations; the same hardware supporting multiple applications. This approach also guarantees the capability of performing high-speed data transfers of up to 100 MHz.  Multiple buffer storage avoids data overlap, protecting data integrity. The same unit is capable of interfacing with communication protocols having baud rates ranging from 12.5 KHz (ARINC) to 100 MHz (AFDX-ARINC 664).

Current Implementation:

The UADI is an intelligent interface, incorporating all of the above features and functionality into its implementation (Figure 3 – System configuration).  It uses a MSP430 microcontroller with  RISC architecture from Texas Instrument’s.  This chip runs on extremely low power, less than 10 mili Amp during operation and micro Amps during stand-by. It combines two asynchronous serial ports, eight 12 bits ADC, multiple general I/O, PWM and timers with an average instruction cycle of 4 MIPS.

The FPGA selected is part of the Xilinx’s Spartan II family, combining all the features defined in the above sections. The FPGA design includes various modules, which manage multiple protocols and/or channels. It takes advantage of the architecture flexibility to include a variety of functions, giving the user an extremely powerful tool.

The UADI combines a variety of ARINC protocols, MIL-STD-11553 and RS232/422. The AFDX is being test and we expect to have it fully operating before the end of this year.

The UADI family of boards support the most popular computer platforms including PCI (picture 4), Compact PCI (Figure 5), PC/104(Figure 6), PMC (Figure 7) and SBC(Figure 8). All are based on the same CPU firmware that includes FPGA software initialization and operational code. Additional ICs are a hardware interface for the different protocols and bus platforms. The simplicity of theses boards creates a powerful low power interface with minimum components and a very high MTBF.

BMC NEW PRODUCT FAMILY:

The CPU and all of the above features and functionality can be incorporated into a single chip result in a single download configuration. All functionalities required for the UADI are available in the Xilinx FPGA platform, the CPU (MicroBlaze soft processor), counters, UARTS, etc. The unit can be easily upgraded has better MTBF and better real time performance.

The device selected was the Spartan-3AN due to it internal flash memory which doesn’t required an external PROM device.

The IP can be recompiled according to the application and is available for other Xilinx FPGA families.

FPGAs make an ideal and cost effective platform for implementing communication protocols like AFDX, ARINC 429 and MIL-STD-1553. They can easily replace and solve the problems associated with the older integrated microcontroller technology. Newer Xilinx FPGA families like the Spartan-3AN can also shrink design footprints, making systems smaller and lighter as well.

BMC sales three product levels: IP, Chips and boards. The products are available with single or multiple protocols and channels. The IP is available with different configurations: with (second phase) or without (first phase) the MicroBlaze microcontroller. The IP is configurable according to customer needs; Xilinx parts and packages.